1. Field of the Invention
The present invention relates to a voltage regulator that is capable of stable operation even under a light load so as to cover a wide range of load capacitances.
2. Description of the Related Art
As a conventional voltage regulator 100, a circuit illustrated in FIG. 7 is known (see, for example, Japanese Patent Application Laid-open No. 1992-195613 (FIG. 1)).
A power supply voltage of a battery 120 is applied between a VDD terminal 121 and a VSS terminal 123. A load 125 and a load capacitor 126 are connected to a VOUT terminal 124.
A reference voltage circuit 101 outputs a constant voltage to be applied to an inverting input terminal of an error amplifier 102. A voltage of the VOUT terminal 124 is divided by means of resistors 104 and 105, and the divided voltage is applied to a non-inverting input terminal of the error amplifier 102. An output transistor 103 has a source connected to the VDD terminal 121, a drain connected to the VOUT terminal 124, and a gate connected to an output of the error amplifier 102. The output transistor 103 accordingly has a resistance controlled based on the output of the error amplifier 102. In other words, the following control is made so that a constant voltage may be output to the VOUT terminal 124. If a voltage determined by dividing the output voltage of the VOUT terminal 124 by means of the resistors 104 and 105 is lower than the output voltage of the reference voltage circuit 101, the output of the error amplifier 102 becomes low to strongly bias the output transistor 103 so that the output transistor 103 may be reduced in resistance to thereby increase the voltage of the VOUT terminal 124. On the other hand, if the voltage determined by dividing the above-mentioned voltage by means of the resistors 104 and 105 is higher than the reference voltage, the output transistor 103 is weakly biased to have a large resistance to thereby reduce the voltage of the VOUT terminal 124.
A CE circuit 110 controls ON/OFF of the voltage regulator based on a voltage applied to a CE terminal 122.
A capacitor 106 is connected in parallel to the resistor 104 and performs phase compensation on the voltage regulator.
FIG. 8A is a circuit focusing on the resistors 104 and 105 and the capacitor 106 of the voltage regulator.
When the voltage of the VOUT terminal 124 and the voltage of a connection point between the resistors 104 and 105 are represented by Vout and Vfb, respectively, a transfer function from the VOUT terminal 124 to the connection point between the resistors 104 and 105 is derived from Expressions (1) to (3).
                              [                      Expression            ⁢                                                  ⁢            1                    ]                ⁢                                                                                                            V            FB                                V            OUT                          =                                            R              2                                                      R                1                            +                              R                2                                              ·                                    1              +                              s                fz                                                    1              +                              s                fp                                                                        (        1        )                                          [                      Expression            ⁢                                                  ⁢            2                    ]                ⁢                                                                                      fz        =                  1                      2            ×            π            ×            Cz            ×                          R              1                                                          (        2        )                                          [                      Expression            ⁢                                                  ⁢            3                    ]                ⁢                                                                                      fp        =                  1                      2            ×            π            ×            Cz            ×                                                            R                  1                                ×                                  R                  2                                                                              R                  1                                +                                  R                  2                                                                                        (        3        )            
where R1 and R2 represent respective resistances of the resistors 104 and 105, and Cz represents a capacitance of the capacitor 106. In other words, there are a zero and a pole, which are derived from Expressions (2) and (3), respectively.
FIGS. 8B and 8C illustrate a gain Bode plot and a phase Bode plot of the transfer function, which is derived from Expression (1). As illustrated in FIG. 8C, as a frequency increases, a phase is advanced from 0 degrees by 45 degrees at a zero frequency fz, and is further advanced to 90 degrees at a maximum. Then, the phase becomes 45 degrees at a pole frequency fp, and returns to 0 degrees again. In other words, the phase advancing effect is exerted in a range from around the frequency fz to around the frequency fp.
FIG. 9 illustrates a Bode plot of the voltage regulator having two poles.
The output terminal 124 of the voltage regulator is connected to the load 125 and the load capacitance 126, and accordingly a pole appears. In a case where the load 125 is light and accordingly the load capacitance 126 is large, the pole appears at low frequency, leading to a narrow bandwidth of the voltage regulator. In addition, there is another pole in the error amplifier 102, and hence a phase is delayed by 180 degrees at low frequency, resulting in no phase margin (phase margin of near 0). In this case, a bandwidth fbw of the voltage regulator is reduced to, for example, approximately 100 Hz.
FIG. 10 illustrates a Bode plot of the voltage regulator having three poles and one zero, which is obtained when appropriate phase compensation is performed by the resistors 104 and 105 and the capacitor 106. A zero (frequency fz) appears around a pole frequency fp2 so that a phase margin of, for example, 30 degrees or more may be secured at a gain of 0 dB or more.
However, the conventional voltage regulator involves a problem of being incapable of stable operation under a light load to cover a wide range of load capacitances.
In order to lower the zero frequency to approximately 100 Hz, as apparent from Expression (2), a time constant Cz×R1 of the order of milliseconds is required. However, in the conventional voltage regulator illustrated in FIG. 7, if the time constant Cz×R1 is of the order of milliseconds, the start-up of the voltage regulator takes a time period of the order of milliseconds after change of the CE terminal voltage from “L” to “H”, as illustrated in FIG. 11B. Therefore, there is another problem that the voltage regulator cannot be used for applications where quick start-up is required.